Electronic circuits are often manufactured as integrated circuits formed by processing silicon wafers. Many such wafers contain individual circuit designs where the individual circuits are replicated in manufacturing processes on a single wafer. The replicated circuits are separated as dies (“chips”) by cutting the wafer in a saw-lane space provided between adjacent replicated circuits. Increasing complexities and applications for circuit designs have led to a relatively broad and varied selection of packages for securing, protecting and coupling individual die. For example, chip-scale technology packaging includes direct surface-mount packages occupying a surface area (e.g., footprint) marginally larger (e.g., 1.2 times larger) than the area of the die. Such constraints have led to increased costs for packages with relatively large numbers of contacts (e.g., pins) and occupying relatively small footprints.